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| 24LC21A 1K 2.5V Dual Mode I2CTM Serial EEPROM Features * Single supply with operation down to 2.5V * Completely implements DDC1TM/DDC2TM interface for monitor identification, including recovery to DDC1 * Pin and function compatible with 24LC21 * Low-power CMOS technology - 1 mA typical active current - 10 A standby current typical at 5.5V * 2-wire serial interface bus, I2CTM compatible * 100 kHz (2.5V) and 400 kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * Page write buffer for up to eight bytes * 1,000,000 erase/write cycles ensured * Data retention > 200 years * ESD Protection > 4000V * 8-pin PDIP and SOIC package * Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C Package Types PDIP NC NC NC VSS SOIC NC NC NC Vss 1 24LC21A 2 3 4 8 7 6 5 Vcc VCLK SCL SDA 1 24LC21A 2 3 4 8 7 6 5 Vcc VCLK SCL SDA Block Diagram HV Generator Description The Microchip Technology Inc. 24LC21A is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-only mode, sending a serial bit stream of the memory array from 00h to 7Fh, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the transition mode, and look for a valid control byte on the I2C bus. If it detects a valid control byte from the master, it will switch into Bidirectional mode, with byte selectable read/write capability of the memory array using SCL. If no control byte is received, the device will revert to the Transmit-only mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LC21A is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges. I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches SDA SCL YDEC VCLK Sense AMP R/W Control VCC VSS Pin Function Table Name VSS SDA SCL VCLK VCC NC Function Ground Serial Address/Data I/O Serial Clock (Bidirectional mode) Serial Clock (Transmit-only mode) +2.5V to 5.5V Power Supply No Connection DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation. 2003 Microchip Technology Inc. DS21160F-page 1 24LC21A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS.........................................................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-65C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +2.5V to 5.5V Commercial (C): TA = 0C to +70C Industrial (I): TA =-40C to +85C Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT ICC Write ICC Read ICCS Min 0.7 VCC -- 2.0 -- .05 VCC -- -- -- -- -- -- -- -- -- Max -- 0.3 VCC -- 0.2 VCC -- 0.4 0.6 1 1 10 3 1 30 100 Units V V V V V V V A A pF mA mA A A VCC 2.7V (Note) VCC < 2.7V (Note) (Note) IOL = 3 mA, VCC = 2.5V (Note) IOL = 6 mA, VCC = 2.5V VIN = 0.1V to VCC VOUT = 0.1V to VCC VCC = 5.0V (Note) TA = 25C, FCLK = 1 MHz VCC = 5.5V VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC VCLK = VSS Conditions DC CHARACTERISTICS Parameter SCL and SDA pins: High-level input voltage Low-level input voltage Input levels on VCLK pin: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note: This parameter is periodically sampled and not 100% tested. DS21160F-page 2 2003 Microchip Technology Inc. 24LC21A TABLE 1-2: AC CHARACTERISTICS Symbol FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Vcc= 2.5-5.5V Standard Mode Min Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc= 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns Units Remarks Parameter (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2) TOF Output fall time from VIH minimum to VIL maximum Input filter spike suppres- TSP sion (SDA and SCL pins) Write cycle time TWR Transmit-Only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW VCLK setup time TVHST VCLK hold time TSPVL Mode transition time TVHZ Transmit-only power-up TVPU time Input filter spike suppres- TSPV sion (VCLK pin) Endurance -- Note 1: 2: 3: 4: -- -- -- -- 4000 4700 0 4000 -- 0 -- 1M 250 50 10 2000 -- -- -- -- 1000 -- 100 -- 20 + 0.1 CB -- -- -- 600 1300 0 600 -- 0 -- 1M 250 50 10 1000 -- -- -- -- 500 -- 100 -- ns ns ms ns ns ns ns ns ns ns ns cycles (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode 25C, Vcc = 5.0V, Block mode (Note 4) Not 100% tested. CB = Total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site. 2003 Microchip Technology Inc. DS21160F-page 3 24LC21A 2.0 FUNCTIONAL DESCRIPTION The 24LC21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bidirectional mode. Otherwise, it will revert to the Transmit-only mode after it sees 128 VCLK pulses. it be initialized prior to valid data being sent in the Transmit-only mode (Section 2.2 "Initialization Procedure"). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmitonly mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-only mode. 2.2 Initialization Procedure 2.1 Transmit-Only Mode The device will power-up in the Transmit-only mode at address 00H. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. This device requires that After VCC has stabilized, the device will be in the Transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). FIGURE 2-1: SCL TRANSMIT-ONLY MODE Tvaa SDA Tvaa Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7 VCLK Tvhigh Tvlow FIGURE 2-2: Vcc SCL DEVICE INITIALIZATION Tvaa High-impedance for 9 clock cycles Tvpu Tvaa Bit 8 Bit 7 SDA VCLK 1 2 8 9 10 11 DS21160F-page 4 2003 Microchip Technology Inc. 24LC21A 3.0 BIDIRECTIONAL MODE Before the 24LC21A can be switched into the Bidirectional mode (Figure 3-1), it must enter the Transition mode, which is done by applying a valid high-to-low transition on the Bidirectional mode Clock (SCL). As soon it enters the Transition mode, it looks for a control byte 1010 000X on the I2CTM bus, and starts to count pulses on VCLK. Any high-to-low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-only mode, and transmit its contents starting with the Most Significant bit in address 00h. However, if it detects the control byte on the I2CTM bus, (Figure 3-2) it will switch to the in the Bidirectional mode. Once the device has made the transition to the Bidirectional mode, the only way to switch the device back to the Transmit-only mode is to remove power from the device. The mode transition process is shown in detail in Figure 3-3. Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I2CTM). In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode Clock (SCL), controls access to the bus and generates the Start and Stop conditions, while the 24LC21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In the Bidirectional mode, the 24LC21A only responds to commands for device 1010 000X. FIGURE 3-1: MODE SCL MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE Transmit Only Bidirectional TVHZ Recovery to Transmit-only mode (MSB of data in 00h) SDA VCLK count = VCLK 1 2 3 4 127 128 Bit8 FIGURE 3-2: Transmit Only mode MODE SCL SDA VCLK count = VCLK SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE Transition mode with possibility to return to Transmit-only mode Bidirectional permanently 1 2 n S1 0 0 1 0 0 0 0 0 ACK n < 128 2003 Microchip Technology Inc. DS21160F-page 5 24LC21A FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA Display Power-on or DDC Circuit Powered from +5 volts The 24LC21A was designed to comply to the portion of flowchart inside dash box Communication is idle Is Vsync present? Yes Send EDID continuously using Vsync as clock No High-to-low transition on SCL? Yes No High-to-low transition on SCL? Yes Stop sending EDID. Switch to DDC2 mode. No DDC2 communication idle. Display waiting for address byte. No DDC2B address received? Yes Display has optional transition state ? Yes Set Vsync counter = 0 or start timer No Reset counter or timer Receive DDC2B command No Change on SCL, SDA or VCLK lines? Yes No High - low transition on SCL ? Yes Reset Vsync counter = 0 Is display Access.busTM capable? Yes Valid Access.bus address? Yes Yes No Respond to DDC2B command No Valid DDC2 address received? No No VCLK cycle? Yes Increment VCLK counter (if appropriate) See Access.bus specification to determine correct procedure. No Counter=128 or timer expired? Yes Switch back to DDC1 mode. Note 1: The base flowchart is copyright 1993, 1994, 1995 Video Electronic Standard Association (VESA) from VESA's Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text "The 24LC21A and... inside dash box." are added by Microchip Technology Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A. DS21160F-page 6 2003 Microchip Technology Inc. 24LC21A 3.1 Bidirectional Mode Bus Characteristics Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. Note: Once switched into Bidirectional mode, the 24LC21A will remain in that mode until power is removed. Removing power is the only way to reset the 24LC21A into the Transmit-only mode. The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-4). 3.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 3.1.5 ACKNOWLEDGE 3.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24LC21A does not generate any Acknowledge bits if an internal programming cycle is in progress. 3.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 3.1.4 DATA VALID (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. FIGURE 3-4: (A) SCL (B) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (D) (D) (C) (A) SDA START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION 2003 Microchip Technology Inc. DS21160F-page 7 24LC21A FIGURE 3-5: BUS TIMING START/STOP SCL THD:STA TSU:STA SDA VHYS TSU:STO START STOP FIGURE 3-6: BUS TIMING DATA TF THIGH TLOW TR SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO TBUF 3.1.6 SLAVE ADDRESS FIGURE 3-7: After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code (1010000) for the 24LC21A. The eighth bit of slave address determines whether the master device wants to read or write to the 24LC21A (Figure 3-7). The 24LC21A monitors the bus for its corresponding slave address continuously. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Read Write Slave Address 1010000 1010000 R/W 1 0 CONTROL BYTE ALLOCATION READ/WRITE START SLAVE ADDRESS R/W A 1 0 1 0 0 0 0 DS21160F-page 8 2003 Microchip Technology Inc. 24LC21A 4.0 4.1 WRITE OPERATION Byte Write 4.2 Page Write Following the start signal from the master, the slave address (four bits), three zero bits (000) and the R/W bit which is a logic low are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC21A. After receiving another acknowledge signal from the 24LC21A the master device will transmit the data word to be written into the addressed memory location. The 24LC21A acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LC21A will not generate acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way as in a byte write. But instead of generating a Stop condition the master transmits up to eight data bytes to the 24LC21A which are temporarily stored in the onchip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-3). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 2003 Microchip Technology Inc. DS21160F-page 9 24LC21A FIGURE 4-1: BYTE WRITE S T A R T S A C K A C K A C K CONTROL BYTE WORD ADDRESS S T O P P BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY DATA VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL SDA IN THD:STA THD:STO VCLK TVHST TSPVL FIGURE 4-3: BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY VCLK S T A R T S PAGE WRITE CONTROL BYTE WORD ADDRESS S T O P P A C K A C K A C K A C K A C K DATA (n) DATA n + 1 DATA n + 7 DS21160F-page 10 2003 Microchip Technology Inc. 24LC21A 5.0 ACKNOWLEDGE POLLING 6.0 WRITE PROTECTION Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for the flow diagram. When using the 24LC21A in the Bidirectional mode, the VCLK pin can be used as a write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LC21A to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-only mode. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Yes Next Operation No 2003 Microchip Technology Inc. DS21160F-page 11 24LC21A 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read except that after the 24LC21A transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24LC21A to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LC21A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.1 Current Address Read The 24LC21A contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC21A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21A discontinues transmission (Figure 7-1). 7.4 Noise Protection The 24LC21A employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SDA, SCL and VCLK inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. FIGURE 7-1: S T A R T CURRENT ADDRESS READ S T O P P A C K N O A C K BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY CONTROL BYTE DATA n S101 00001 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC21A as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC21A will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21A discontinues transmission (Figure 7-2). DS21160F-page 12 2003 Microchip Technology Inc. 24LC21A FIGURE 7-2: RANDOM READ S T A R T S T A R T S T O P P A C K N O A C K BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY CONTROL BYTE WORD ADDRESS CONTROL BYTE DATA n S1 01 0000 0 A C K A C K S10100001 FIGURE 7-3: BUS ACTIVITY MASTER CONTROL BYTE SDA LINE A C K SEQUENTIAL READ DATA n+2 DATA n+X S T O P P A C K A C K A C K N O A C K DATA n DATA n+1 BUS ACTIVITY 2003 Microchip Technology Inc. DS21160F-page 13 24LC21A 8.0 8.1 PIN DESCRIPTIONS SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 K for 100 kHz, 2 K for 400 kHz). For normal data transfer in the Bidirectional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 8.2 SCL This pin is the clock input for the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-only mode. 8.3 VCLK This pin is the clock input for the Transmit-only mode (DDC1). In the Transmit-only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. DS21160F-page 14 2003 Microchip Technology Inc. 24LC21A APPENDIX A: Revision F Corrections to Section 1.0, Electrical Characteristics. REVISION HISTORY 2003 Microchip Technology Inc. DS21160F-page 15 24LC21A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Device 24LC21A 24LC21AT Dual Mode Serial EEPROM Dual Mode Serial EEPROM (Tape and Reel) Temperature Range Blank I 0C to -40C to +70C +85C Package P SN = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21160F-page 16 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS21160F-page 17 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 China - Beijing Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Atlanta 3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307 Taiwan Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 China - Fuzhou Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 EUROPE Austria Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 China - Hong Kong SAR Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Denmark Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910 China - Shanghai Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387 France Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393 Germany Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Phoenix 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Shunde Room 401, Hongjian Building No. 2 Fengxiangnan Road, Ronggui Town Shunde City, Guangdong 528303, China Tel: 86-765-8395507 Fax: 86-765-8395571 Italy Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 San Jose 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Qingdao Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Netherlands P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS21160F-page 18 2003 Microchip Technology Inc. |
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